The Onyx®, Xilinx Virtex-7 FPGA family uses the latest Xilinx FPGA technology to provide customers additional processing engines with the lowest power to address the insatiable demand of higher-speed A/Ds and D/As and tougher DSP algorithms.
The Onyx Architecture
All of the board’s data and control paths are accessible by the FPGA, enabling factoryinstalled functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx architecture organizes the FPGA as a container for data processing applications where each function exists as an (IP) module.
An internal timing bus provides board timing and synchronization. The bus includes a clock, sync and gate or trigger signals. A Clock/Sync connector allows multiple boards to be synchronized. Multiple boards can be driven from the bus master, thereby supporting synchronous sampling and sync functions across all connected boards.